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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
5.13 Universal Asynchronous Receiver/Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from an external peripheral device and
parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.
The device has one UART peripheral with the following features:
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Programmable baud rates (frequency pre-scale values from 1 to 65535)
Fully programmable serial interface characteristics:
– 5, 6, 7, or 8-bit characters
– Even, odd, or no PARITY bit generation and detection
– 1, 1.5, or 2 STOP bit generation
16-byte depth transmitter and receiver FIFOs:
– The UART can be operated with or without the FIFOs
– 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
CPU interrupt capability for both received and transmitted data
False START bit detection
Line break generation and detection
Internal diagnostic capabilities:
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
Programmable autoflow control using CTS and RTS signals
5.13.1 UART Peripheral Register Descriptions
Table 5-29. UART Registers
HEX ADDRESS
RANGE
1B00h
1B00h
1B02h
1B04h
1B04h
1B06h
1B08h
1B0Ah
1B0Ch
1B0Eh
1B10h
1B12h
1B18h
ACRONYM
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLH
PWREMU_MGMT
REGISTER NAME
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register
Divisor LSB Latch
Divisor MSB Latch
Power and Emulation Management Register
116
Peripheral Information and Electrical Specifications
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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